1. Technology Field
The present invention relates to a clock generator. More particularly, the present invention relates to a pseudo random clock generator having a code limiter.
2. Related Art
Due to increases in the speed at which digital circuits operate, clock circuits that generate reference clocks for digital circuits have to operate at higher frequencies, for example in the 100 MHz range. An artifact of higher frequency clocks circuits is that electromagnetic interference (EMI) emissions as a result of clock signal transmissions can significantly exceed the level of thermal noise.
One technique to reduce the EMI emissions when transmitting a clock signal is to spread the clock frequency by modulation of the clock period, which is known as Spread spectrum clocking (SSC) technique. This technique is known as spread spectrum clocking. The spread is about 0.25-1.5% of the center frequency, and helps to reduce the peak of the emission at the center of frequency. However, the spread spectrum clock still emits electromagnetic interference.
FIG. 1 illustrates a pseudo random (PN) generator that spreads the clock over a wide spectrum. The generator 100 includes a shift register 101, a first XOR gate 102 and a second XOR gate 103. The shift register 101 is a 10-bit shift register. The shift register 101 receives a clock signal OCLK and the feedback signal from the first XOR gate 102 and delivers the output signal to the first XOR gate 102 such that the first XOR gate 102 outputs a pseudo random code PN. The second XOR gate 103 receives the pseudo random code PN and the clock signal OCLK, and outputs a pseudo random clock having the similar frequency as that of the clock signal OCLK accordingly.
FIG. 2 to FIG. 4 illustrate the timing charts of the pseudo random generator of FIG. 1. In FIG. 2, the frequency of the pseudo random clock is the same as that of the original frequency. In FIG. 3, the frequency of the pseudo random clock is half of the original frequency. In FIG. 4, the frequency of the pseudo random clock is ⅔ of the original frequency. It is noted that the frequency of pseudo random clock is affected by the pseudo random code since the pseudo random clock is the exclusive OR operation result of the pseudo random code and the original clock.
FIG. 5 is Fast Fourier Transform (FFT) simulation of the circuitry of FIG. 1. The curve 110 represents a clock in form of sine wave. The curve 120 represents the spread-spectrum signal by way of conventional art. The curve 130 represents the spread-spectrum signal by way of the circuitry in FIG. 1. The result shows 30.19 dB reduction in peak power-density that is better than analog circuit implementation. The frequency of the spread-spectrum clock is ½ to 1 time of the original clock. It is noted that the wide spread spectrum may restrain the power density; however, the spread spectrum bandwidth is somewhat broad.
Even though the prior art in FIG. 1 may reduce the EMI emissions, the large spread bandwidth has influence on the AC to DC system, like noisy power, or lower switching frequency, etc. This leads to difficulty to design parameters in a power system. Even though a digital to analogs converter may by employed to limit the frequency range, the material cost is also considerable.